1. Field of the Invention
The present invention relates to a data demultiplexer, and more particularly to a data demultiplexer for reproducing and separating video and audio data that are recorded in a time-division multiplex fashion on a recording medium such as an optical disk, for example.
2. Description of the Related Art
FIGS. 3A and 3B of the accompanying drawings illustrates in block form a conventional data demultiplexer and associated circuits. As shown in FIGS. 3A and 3B, a drive unit 1 reproduces data recorded on a built-in optical disk (not shown). The optical disk stores video and audio data that are recorded in a time-division multiplex fashion. The reproduced data outputted from the drive unit 1 is supplied to and demodulated by a demodulator 2. Errors contained in the demodulated data outputted from the demodulator 2 are detected and corrected by an ECC (Error Correcting Code) circuit 3, which supplies error-corrected data to a ring buffer 4. The ring buffer 4 stores a predetermined amount of supplied data, and then outputs the stored data to a data demultiplexer 5.
The data demultiplexer 5 has a data separator 21 for separating video data and audio data from the data supplied from the ring buffer 4. Data separator 21 also acts to separate SCR (System Clock Reference) data as timing data, and DTS (Decoding Time Stamp) data in the form of video data (DTSV) and audio data (DTSA) from the data supplied from ring buffer 4.
The separated video data is supplied to a video code buffer 6 of an FIFO (First-In, First-Out) configuration. The separated audio data is supplied to an audio code buffer 8 of an FIFO configuration. The SCR data is supplied to and stored in an STC (System Time Clock) register 26. The STC register 26 counts clock pulses having a frequency of 90 kHz which are outputted from a clock generator 27, and increments the stored data to generate an STC signal.
The DTSV and DTSA data are supplied to and stored in respective DTSV, DTSA registers 22, 24. The DTSV and DTSA data stored in the respective DTSV, DTSA registers 22, 24 are supplied to respective comparators 23, 25 for comparison with the STC signal outputted from the STC register 26. The data demultiplexer 5 also has a control circuit 28 comprising a CPU or the like for controlling the data separator 21 based on commands that are inputted from an input unit 29 in response to operations made by the user.
The video data stored in the video code buffer 6 is read and supplied to a video decoder 7. The video decoder 7 decodes the supplied video data into a video signal which is outputted to a circuit (not shown). The video decoder 7 is supplied with a video decoding start signal outputted from the comparator 23.
Similarly, the audio data stored in the audio code buffer 8 is read and supplied to an audio decoder 9. The audio decoder 9 decodes the supplied audio data into an audio signal which is outputted to a circuit (not shown). The audio decoder 9 is supplied with an audio decoding start signal outputted from the comparator 25.
Operation of the conventional data demultiplexer 5 will be described below with reference to FIG. 5 of the accompanying drawings. When the user operates the input unit 29 to issue a command to start reproducing data recorded on the built-in optical disk, the drive unit 1 reproduces the recorded data. The reproduced data outputted from the drive unit 1 is supplied to the demodulator 2 which demodulates the supplied data. The demodulated data is supplied to the ECC circuit 3 for detecting and correcting errors contained in the demodulated data. The error-corrected data is then supplied through the ring buffer 4 to the data separator 21 of the data demultiplexer 5.
The data supplied to the data demultiplexer 5 has a format stipulated as shown in FIG. 4 of the accompanying drawings, for example. The data format is stipulated as a multiplexed bit stream of MPEG (Moving Picture Expert Group) that is stipulated according to the ISO (International Standardization Organization), 11172. As shown in FIG. 4, the multiplexed bit stream is composed of one or more packs, each comprising one or more packets. The pack includes a pack header at its starting end which includes a pack start code indicative of a starting point of the pack an SCR, and a MUX RATE. The SCR represents the time at which its final byte is inputted to the data demultiplexer 5. The MUX RATE represents a transfer rate.
In the data format shown in FIG. 4, the pack header is followed by a video packet and an audio packet. Each of these video and audio packets includes a packet header at its starting end, which includes a video packet start code indicative of a starting point of the video packet or an audio packet start code indicative of a starting point of the audio packet, and a DTSV or DTSA indicative of the time at which the video or audio data starts to be decoded. The packet header is followed by video data or audio data.
Each of the timing data SCR, DTSV, DTSA is expressed by the count of clock pulses at the frequency of 90 kHz, and has a 33-bit effective number.
The data separator 21 is controlled by the control circuit 28 for separating video data and audio data from the data supplied from the ring buffer 4, and supplies the video data to the video code buffer 6 and the audio data to the audio code buffer 8, and also separating the SCR, DTSV, DTSA data and supplying them to the STC register 26, the DTSV register 22, and the DTSA register 24, respectively, which store the supplied data.
The STC register 26 stores the SCR data, subsequently counts clock pulses outputted from the clock generator 27, and increments the stored data in response to the clock pulses. The stored data is supplied as internal time data (STC) from the STC register 26 to the comparators 23, 25.
The SCR data corresponds to the time at which the data is supplied from the ring buffer 4 to the data demultiplexer 5 and starts to be demultiplexed thereby. That is, the SCR data corresponds to a time t1 in the timing chart shown in FIG. 5. The STC register 26 outputs time data (present time) indicative of the time that has elapsed from the time t1 to one of the input terminals of each of the comparators 23, 25.
The DTSV register 22 supplies the time data DTSV indicative of the time at which the video decoder 7 starts decoding the video data to the other input terminal of the comparator 23. When the present time outputted from the STC register 26 agrees with the decoding start time (DTSV) outputted from the DTSV register 22, i.e., at a time t2 in FIG. 5, the comparator 23 outputs a video decoding start signal to the video decoder 7. In response to the supplied video decoding start signal, the video decoder 7 reads one frame of stored video data from the video code buffer 6, and starts decoding the frame of video data.
In FIG. 5, the straight line A represents the state of writing the video data into the video code buffer 6, and its gradient represents the writing transfer rate. The polygonal line B represents the state of reading the video data from the video code buffer 6 into the video decoder 7. Therefore, the video data which remains stored in the video code buffer 6 is indicated by the shaded area. The straight line C represents the time by which the video data written in the video code buffer 6 at timing of the straight line A is required to be read. Other video data is written in the video code buffer 6 at the timing of the straight line C. The storage capacity of the video code buffer 6 is indicated by the vertical distance up to the straight lines A, C.
In response to the video decoding start signal, the video decoder 7 starts decoding the video data. When the video decoder 7 completes the decoding of the video data, i.e., upon elapse of a video decode delay (VIDEO.sub.-- DECODE.sub.-- DELAY) from the start of the decoding of the video data, the video decoder 7 generates a video synchronizing signal, and then outputs a video signal to the non-illustrated circuit for image display. Thus, after elapse of the video decode delay from the start of the decoding of the video data, an image represented by the video signal is displayed. Therefore, as shown in FIG. 5, the video synchronizing signal can be outputted at intervals different from those prior to the time t2.
Likewise, the comparator 25 outputs an audio decoding start signal when the present time outputted from the STC register agrees with the decoding start time, at which the audio data starts to be decoded, outputted from the DTSA register 24. In response to the supplied audio decoding start signal, the audio decoder 9 reads stored audio data from the audio code buffer 8, and starts decoding the audio data to generate an audio signal. Then, the audio decoder outputs the audio signal to the non-illustrated circuit for sound playback.
In the conventional data demultiplexer, each time the video decoder 7 starts decoding the video data, it generates a video synchronizing signal regardless of the video synchronizing signal that has been outputted so far, and outputs a video signal with the generated video synchronizing signal added thereto. Therefore, the video synchronizing signal tends to be disturbed after the video decoder 7 starts to decode the video data, with the result that the displayed image tends to become unsightly.
One solution would be to record a video signal decoded by the video decoder 7 in a new buffer connected to the video decoder 7, and read the video signal from the buffer in timed relationship to a video synchronizing signal supplied from an external source, so that video synchronizing signals can be supplied at regular intervals for stably displaying an image based on the video signal. However, the scale of the circuit required is increased because a large-capacity buffer is required to record a decoded video signal.